Device leakage is a challenge for the design and operation of non-volatile memories such as erasable programmable read only memories (EPROMs), electrically erasable programmable read only memories (EEPROMs), and block-erasable EEPROMs (e.g., “flash” memories), etc. Device leakage increases the loads on the supply components, such as charge pumps, within a non-volatile memory (NVM) module and can lead to degraded performance. Another problem is reduced signal-to-noise immunity at low voltage due to low-voltage drive-strength roll off. Moreover, the transconductance degradation of memory cells with cycling can be significant, especially with smaller cell sizes.
For erase procedures, increased device leakage may cause significant loading on charge pumps that are used to supply erase biases. As a result, memory cells may receive inefficient erase pulse bias levels, and may fail to erase. For program procedures, increased column leakage may cause significant loading on drain charge pumps. As a result, memory cells may receive very inefficient program pulse bias levels, and may fail to be properly programmed.